Methods of forming DRAM cells

ABSTRACT

The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM substructures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which comprises a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

TECHNICAL FIELD

[0001] The invention pertains to DRAM cell constructions and methods offorming DRAM cells.

BACKGROUND OF THE INVENTION

[0002] Technologies referred to as “smart cut” and “wafer-bonding” havebeen utilized to bond monocrystalline silicon materials ontosemiconductor substrates. Smart cut technology generally refers to aprocess in which a material is implanted into a silicon substrate to aparticular depth and ultimately utilized to crack the substrate, andwafer bonding technology generally refers to a process in which a firstsemiconductive substrate is bonded to a second semiconductor substrate.

[0003] In particular applications of smart cut and wafer-bondingtechnology, hydrogen ions (which can be, for example, H⁺, H₂ ⁺, D⁺, D₂⁺) are implanted into a first monocrystalline silicon substrate to adesired depth. The first monocrystalline silicon substrate comprises asilicon dioxide surface, and is bonded to a second monocrystallinesubstrate through the silicon dioxide surface. Subsequently, the bondedfirst substrate is subjected to a thermal treatment which causescleavage along the hydrogen ion implant region to split the firstsubstrate at a pre-defined location. The portion of the first substrateremaining bonded to the second substrate can then be utilized as asilicon-on-insulator (SOI) substrate. An exemplary process is describedin U.S. Pat. No. 5,953,622. The SOI substrate is subsequently annealedat a temperature of greater than or equal to 900° C. to strengthenchemical coupling within the second substrate.

[0004] The present invention encompasses new applications for smart cutand wafer-bonding technology, and new semiconductor structures which canbe created utilizing such applications.

SUMMARY OF THE INVENTION

[0005] In one aspect, the invention encompasses a method of forming aDRAM cell. A first substrate is formed to comprise first DRAMsubstructures separated from one another by an insulative material. Asecond semiconductor substrate provided which comprises amonocrystalline material. The second semiconductor substrate is bondedto the first substrate after forming the first DRAM sub-structures.Second DRAM sub-structures are formed on either the first substrate orthe second substrate and in electrical connection with the first DRAMsub-structures. Either the first DRAM sub-structures or the second DRAMsub-structures are transistor gate structures, and the other of thefirst and second DRAM sub-structures are capacitor structures.

[0006] In another aspect, the invention encompasses another method offorming a DRAM cell. A first substrate is formed to comprise first DRAMsub-structures separated from one another by an insulative material. Thefirst DRAM sub-structures define an upper surface. A secondsemiconductor substrate is provided which comprises a monocrystallinematerial. The second semiconductor substrate is bonded to the firstsubstrate above the first DRAM sub-structures. Second DRAMsub-structures are formed on the second substrate and in electricalconnection with the first DRAM sub-structures. Either the first DRAMsub-structures or the second DRAM sub-structures are transistor gatestructures, and the other of the first and second DRAM sub-structuresare capacitor structures.

[0007] In yet another aspect, the invention encompasses a semiconductorstructure which comprises a cell plate layer, a dielectric material overthe cell plate layer, and a conductive storage node mass over thedielectric material. The conductive storage node mass, dielectricmaterial and cell plate layer together define a capacitor structure, anda first substrate is defined to encompass the capacitor structure. Thesemiconductor structure further comprises a monocrystalline siliconsubstrate bonded to the first substrate and over the storage node mass.Additionally, the semiconductor structure comprises a transistor gate onthe monocrystalline silicon substrate and operatively connected with thecapacitor structure to define a DRAM cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment at a preliminary processing step of a first embodimentmethod of the present invention.

[0010]FIG. 2 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 1.

[0011]FIG. 3 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 2.

[0012]FIG. 4 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 3.

[0013]FIG. 5 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 4.

[0014]FIG. 6 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 5.

[0015]FIG. 7 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 6.

[0016]FIG. 8 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 7.

[0017]FIG. 9 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 8.

[0018]FIG. 10 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 9.

[0019]FIG. 11 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 10.

[0020]FIG. 12 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 11.

[0021]FIG. 13 is a view of a wafer fragment at a preliminary processingstep of a second method of the present invention.

[0022]FIG. 14 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 13.

[0023]FIG. 15 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 14.

[0024]FIG. 16 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 15.

[0025]FIG. 17 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 16.

[0026]FIG. 18 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 17.

[0027]FIG. 19 is a view of the FIG. 13 wafer fragment shown at aprocessing step subsequent to that of FIG. 18.

[0028]FIG. 20 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment at a preliminary step of a third embodiment method of thepresent invention.

[0029]FIG. 21 is a view of the FIG. 20 wafer fragment at a processingstep subsequent to that of FIG. 20.

[0030]FIG. 22 is a view of the FIG. 20 wafer fragment shown at aprocessing step subsequent to that of FIG. 21.

[0031]FIG. 23 is a view of the FIG. 20 wafer fragment shown at aprocessing step subsequent to that of FIG. 22.

[0032]FIG. 24 is a view of the FIG. 20 wafer fragment shown at aprocessing step subsequent to that of FIG. 23.

[0033]FIG. 25 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment at a preliminary step of a fourth embodiment method ofthe present invention.

[0034]FIG. 26 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 25.

[0035]FIG. 27 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 26.

[0036]FIG. 28 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 27.

[0037]FIG. 29 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 28.

[0038]FIG. 30 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 29.

[0039]FIG. 31 is a view of the FIG. 25 wafer fragment shown at aprocessing step subsequent to that of FIG. 30.

[0040]FIG. 32 is a view of the FIG. 25 wafer fragment shown invertedrelative to FIG. 25, and at a processing step subsequent to that of FIG.31.

[0041]FIG. 33 is a view of the FIG. 25 wafer fragment shown in the sameorientation as FIG. 32, and at a processing step subsequent to that ofFIG. 32.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0043] A first embodiment method of the present invention is describedwith reference to FIGS. 1-12. Referring first to FIG. 1, a firstsemiconductor structure 10 is illustrated. Structure 10 comprises asemiconductive material wafer 12. Wafer 12 can comprise, for example,monocrystalline silicon lightly doped with a background p-type dopant.To aid in interpretation of the claims that follow, the terms“semiconductive substrate” and “semiconductor substrate” are defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0044] An insulative material 14 is formed over wafer 12. It is notedthat for purposes of interpreting this disclosure and the claims thatfollow, the spacial reference terms “over”, “above”, “beneath” and thelike are utilized to describe relative orientations of variouscomponents to one another. The terms are not utilized in an absolute andglobal sense relative to any external reference. Accordingly, a firstmaterial recited as being “beneath” a second material defines areference of the two materials to one another, but does not mean thatthe first material would actually be “under” the second materialrelative to any reference external of the two materials.

[0045] Insulative material 14 can be referred to as an insulativematerial base, and can comprise, for example, a layer of silicondioxide.

[0046] A conductive material 16 is formed over layer 14. Material 16 cancomprise, for example, metal, silicide, and/or conductively-dopedsilicon (such as, for example, conductively doped polysilicon).

[0047] Referring next to FIG. 2, an insulative material 18 is formedover conductive material 16. Insulative material 18 can comprise, forexample, borophosphosilicate glass (BPSG), and can be formed to athickness of, for example, from about 2 microns to about 4 microns.Openings 20 are formed within insulative material 18 to extend throughinsulative material 18 and to conductive material 16.

[0048] A conductive material 22 is formed over an upper surface ofmaterial 18 and within openings 20. Conductive material 22 can comprise,for example, metal, silicide, and/or conductively-doped silicon, and canhave the same chemical composition as conductive material 16, or bedifferent in chemical composition from conductive material 16.

[0049] In the shown embodiment, conductive material 22 is provided toonly partially fill openings 20. Accordingly, conductive material 22defines two conductive projections 24 and 26 within one of the openings20, and defines another two conductive projections 28 and 30 withinanother of the openings 20. The conductive projections 24, 26, 28 and 30extend substantially vertically from an upper surface of conductivematerial 16. Conductive projections 24, 26, 28 and 30 are in electricalcontact with conductive material 16, and in the shown embodiment areformed on conductive material 16.

[0050] Conductive material 22 narrows the openings 20. A protectivematerial 32 is formed within the narrowed openings and to a levelapproximately equal with an elevational level of an upper surface ofinsulative material 18. Protective material 32 can comprise, forexample, photoresist, and is shown formed to elevational level that isabove that of the upper surface of insulative material 18.

[0051] Referring to FIG. 3, fragment 10 is subjected to planarizationwhich removes material 22 from over an upper surface of insulativematerial 18, while leaving the conductive material 22 within openings20. The protective material 20 (FIG. 2) prevents conductive particles ofmaterial 22 from falling within openings 20 during the planarization. Anexemplary planarization process is chemical-mechanical planarization.After the planarization, protective material 32 is removed from withinthe openings. If material 32 comprises photoresist, such removal couldcomprise, for example, ashing of the photoresist. The portions ofconductive material 22 within openings 20 define conductive containerstructures 23 and 25.

[0052] Referring to FIG. 4, an insulative material 40 is formed overinsulative material 18 and within openings 20. Insulative material 40can comprise, for example, silicon dioxide.

[0053] A patterned masking layer 42 is provided over insulative material40. Patterned masking layer 42 can comprise, for example, photoresistwhich has been patterned by photolithographic processing.

[0054] Referring to FIG. 5, a pattern is transferred from patternedmasking layer 42 to insulative material 40 to form patterned blocks 41of insulative material 40 supported on insulative material 18, as wellas to leave portions of insulative material 40 within openings 20.

[0055] The processing of FIG. 5 represents a partial etch intoinsulative materials 18 and 40. In particular embodiments, insulativematerials 18 and 40 can comprise the same composition as one another,and can, for example, both comprise silicon dioxide. Accordingly, theetch of material 40 shown in FIG. 5 can be extended into material 18 asshown in FIG. 6 to remove material 18 from adjacent sidewalls ofprojections 24, 26, 28 and 30. Preferably, the etch utilized in FIGS. 5and 6 is an etch selective for the insulative materials 18 and 40relative to the conductive material 22. If conductive material 22comprises conductively doped silicon and insulative materials 18 and 40comprise silicon dioxide, a suitable etch can be, for example,fluorocarbon chemistry.

[0056] After the etch of material 18 from along sidewalls of projections24, 26, 28 and 30, sidewall portions 25, 27, 29 and 31 are exposed. Theprojections thus comprise exposed top surfaces and sidewall surfaces.Photoresist 42 (FIG. 5) is subsequently removed, and a dielectricmaterial 44 is deposited over insulative materials 40 and 18, as well asover the exposed top surfaces and sidewall surfaces of conductiveprojections 24, 26, 28 and 30. The dielectric material 44 extends alongsidewall portions 25, 27, 29 and 31 of conductive projections 24, 26, 28and 30, as well as within a narrowed openings 20 (i.e., betweenconductive projections 24 and 26, and between conductive projections 28and 30). Dielectric material 44 can comprise, for example, one or moreof silicon dioxide, silicon nitride, or other dielectric materials. In aparticular embodiment, dielectric material 44 can comprise a layer ofsilicon nitride between two layers of silicon dioxide.

[0057] Referring to FIG. 7, a first storage node mass 46 is formed overconductive projections 24 and 26, and a second storage node mass 48 isformed over conductive projections 28 and 30. Storage node masses 46 and48 are spaced from the conductive material 22 of projections 24, 26, 28and 30 by dielectric material 44. Storage node masses 46 and 48 cancomprise, for example, conductive materials such as metal, silicide,and/or conductively-doped silicon (such as, for example,conductively-doped polysilicon). The shown storage mass structures 46and 48 can be formed by, for example, forming a conductive material overinsulative materials 40 and 18, as well as over the dielectric material44 of the FIG. 6 construction, and subsequently subjecting structure 10to planarization (such as, for example, chemical-mechanical polishing).The planarization removes the conductive material from over insulativemass 40, and thus forms electrically isolated storage node masses 46 and48 from the conductive material.

[0058] Storage node mass 46, together with projections 26 and 28, anddielectric material 44, defines a first capacitor construction 50.Storage node mass 48 together with projections 28 and 30, and dielectricmaterial 44, defines a second capacitor structure 52.

[0059] Referring to FIG. 8, a patterned masking material 54 is providedover portions of storage node masses 46 and 48, while leaving otherportions of the masses exposed. Masking layer 54 can comprise, forexample, photoresist which is patterned by photolithographic processing.After formation of patterned masking layer 54, fragment 10 is subjectedto an etch which etches conductive material 46 selectively relative toinsulative materials 44 and 40. If conductive material 46 comprisesconductively-doped silicon, and insulative materials 44 and 40 comprisesilicon dioxide and/or silicon nitride, a suitable etch can comprise,for example, fluorocarbon chemistry. The etching forms trenches 56 and58 extending into upper surfaces of storage node masses 46 and 48,respectively.

[0060] Referring to FIG. 9, patterned masking layer 54 (FIG. 8) isremoved. Subsequently, an insulative material 60 is formed over storagenode masses 46 and 48 and within trenches 56 and 58. Insulative material60 can comprise, for example, silicon dioxide, or alternatively canconsist of, or consist essentially of, silicon dioxide.

[0061] Referring to FIG. 10, fragment 10 is subjected to fine controlplanarization to form a planarized upper surface 62, and to removeinsulative material 60 from over upper surfaces of storage node masses46 and 48 while leaving insulative material 60 within trenches 56 and58. The insulative material within trenches 56 and 58 defines dopantbarrier regions 64 and 66, respectively. Dopant barrier regions 64 and66 can inhibit out-diffusion of dopant upwardly from storage node masses46 and 48. The insulative material within regions 64 and 66 can bereferred to as an ultra-thin dopant barrier material. It is noted thatalthough the dopant barrier material is referred to above as aninsulative material, the invention also encompasses embodiments in whichthe dopant barrier material is a conductive material.

[0062] Referring to FIG. 11, a silicon-containing layer 70 is formedover storage node masses 46 and 48, as well as over dopant barrierregions 64 and 66. Silicon-containing layer 70 can comprise, forexample, undoped amorphous silicon, and is preferably provided to befrom about 50 Å thick to about 100 Å thick. Silicon-containing layer 70can also consist essentially of amorphous silicon or consist ofamorphous silicon. The undoped amorphous silicon can ultimately functionas a bonding surface in the methodology described herein. Amorphoussilicon typically deposits in a relatively planar form, and accordinglythe thin amorphous silicon layer 70 can be deposited directly overplanarized surface 62 to form a thin layer of amorphous silicon having asubstantially planar top surface. Alternatively, layer 70 can beprovided to be thicker than 100 Å, and subsequently reduced to about 100Å thick or less by chemical-mechanical polishing to form a planarizedtop surface of the amorphous silicon.

[0063] Layer 70 is preferably provided to be undoped (in other wordsresistive). If layer 70 were not resistive, it would form a shortbetween adjacent storage nodes 46 and 48. Dopant diffusion regions 64and 66 prevent out-diffusion of dopant from storage node masses 46 and48 into the region of amorphous silicon layer 70 extending betweenconductive masses 46 and 48.

[0064] A second monocrystalline silicon base 72 is bonded tosilicon-containing layer 70. Such bonding can be accomplished by, forexample, annealing at a temperature of from about 500° C. to about 750°C. for a time of from about 1 minute to about 3 hours. It is noted thatalthough base 72 is referred to as a monocrystalline silicon base, theinvention encompasses embodiments wherein base 72 comprises othersemiconductive materials either alternatively or in addition tomonocrystalline silicon, such as, for example, monocrystallinegermanium. Base 72 can have a damage region therein (not shown) and becleaved by smart cut technology subsequent to bonding base 72 to layer70. If base 72 is cleaved by smart cut technology, it is preferablysubsequently planarized after such cleavage. If base 72 comprises adamage region which is subsequent cleaved, the cleavage can occur eitherabove or below sub-assemblies formed on base 72. Base 72 can alsocomprise a monocrystalline material that does not have a damage regiontherein, and which is accordingly not cleaved by smart cut technology.

[0065] It is noted that storage node masses 46 and 48 together with thematerials therebeneath and oxide layers 40 and 18 can be considered todefine a first semiconductor substrate 80, and base 72 can be consideredto define a second semiconductor substrate 82 bonded atop the firstsemiconductor substrate. Alternatively, the first semiconductorsubstrate can be considered to comprise amorphous silicon layer 70, incombination with the materials thereunder.

[0066] Referring to FIG. 12, transistor devices 100 and 102 are formedover and within semiconductive material base 72. Transistor devices 100and 102 comprise a gate oxide layer 104, a conductive material layer 106and an insulative material layer 108. Conductive material layer 106 cancomprise one or more conductive materials, such as, for example, a stackof metal and/or silicide over conductively-doped polysilicon. Insulativematerial 108 can comprise, for example, silicon nitride or silicondioxide. Gate oxide layer 104 can comprise silicon dioxide. Lightlydoped source/drain regions 110, 112 and 114 are implanted proximategates 100 and 102. Source/drain regions 110, 112 and 114 can beimplanted utilizing gates 100 and 102 as masks, and are doped to aconcentration of from about 10¹⁷ atoms/cm³ to about 10²¹ atoms/cm³. Thesource/drain regions can comprise n-type or p-type dopant. In the shownembodiment, they comprise n-type dopant.

[0067] After forming source/drain regions 110, 112 and 114; insulativesidewall spacers 116 are formed along sidewalls of the gates oftransistor devices 100 and 102. Sidewall spacers 116 can be formed by,for example, depositing an insulative material and subsequentlyanisotropically etching the material. Suitable insulative materials are,for example, silicon dioxide and silicon nitride.

[0068] Base 72 is preferably processed prior to formation of transistordevices 100 and 102 to form insulative oxide regions 130, channelimplant regions 132 and 134, and heavily doped source/drain regions 136,138 and 140.

[0069] The formation of oxide regions 130 can be accomplished by, forexample, forming trenches within base 72 at locations wherein oxideregions 130 are ultimately to be formed, and subsequently filling thetrenches with silicon dioxide. The trenches can be formed by providing apatterned mask to protect regions of base 72 while etching other regionsof base 72 to remove such other regions and form the trenches therein.

[0070] Doped regions 132, 136, 138, 134 and 140 can be formed byimplanting dopants into base 72 and/or by removing portions of base 72and subsequently refilling the portions with conductively-dopedsemiconductive material. For instance, doped regions 136, 138 and 140can be formed by implanting n-type dopant throughout base 72.Alternatively, regions 136, 138 and 140 can be formed by removingportions of base 72 to form trenches at locations wherein regions 136,138 and 140 are ultimately to be formed, and subsequently filling thetrenches with heavily-doped semiconductive material, (such as, forexample, heavily doped polysilicon, with “heavily doped” referring to adopant concentration of at least about 10¹⁸ atoms/cm³). In the shownembodiment, regions 136, 138 and 140 are doped with n-type dopant. It isto be understood, however, that source/drain regions 136, 138 and 140could alternatively comprise p-type doped regions. Also, althoughregions 132 and 134 are shown doped with p-type dopant, it is to beunderstood that the invention encompasses other embodiments wherein oneor both of regions 132 and 134 is doped with n-type dopant.

[0071] Transistor structures 100 and 102, together with capacitorconstructions 50 and 52 comprise a pair of DRAM cells. Specifically, oneof the cells comprises transistor 100 in combination with capacitor 50,while another of the cells comprises transistor 102 in combination withcapacitor 52. Source/drain regions 112 and 138 comprises a bit linecontact for the DRAM cells.

[0072] Transistors 100 and 102 can be considered to be DRAMsubassemblies formed over base 72, and capacitors 50 and 52 can beconsidered DRAM sub-assemblies formed between base 12 and base 72.

[0073] It is noted that in the shown construction the source/drainregions 136 and 140 are vertically extending through base 72 and overstorage node masses 46 and 48. Particularly, it is noted thatsource/drain regions 136 and 140 are directly over storage node masses46 and 48, respectively; with the term “directly over” indicating thatthe conductive regions extend vertically over portions of storage nodemasses 46 and 48. Source/drain regions 136 and 140 can be electricallyconnected with storage node masses 46 and 48 by out-diffusing dopantfrom regions 136 and 140 into silicon-containing layer 70 to formconductively doped regions within layer 70. Such conductively-dopedregions can be conductive interconnects which extend from storage nodemasses 46 and 48 to source/drain regions 136 and 140, and which thuselectrically connect the source/drain regions with the storage nodemasses. It is noted that although source/drain regions 136 and 140 areshown terminating above silicon-containing layer 70, the inventionencompasses other embodiments (not shown) wherein the heavily dopedsource/drain regions extend through silicon-containing layer 70.

[0074] Another embodiment of the invention is described with referenceto FIGS. 13-19. In describing the embodiment of FIGS. 13-19, similarnumbering will be used as was used above in describing the embodiment ofFIGS. 1-12, with the suffix “a” used to indicate structures in FIGS.13-19.

[0075] Referring initially to FIG. 13, a fragment 10 a comprises a base12 a, an insulative layer 14 a, and a conductive layer 16 a. Structures12 a, 14 a and 16 a can comprise the same materials as structures 12, 14and 16 of FIG. 1.

[0076] A patterned insulative material 18 a is formed over layer 16 a.Patterned insulative material 18 a can comprise the same material asinsulative material 18 of FIG. 1, and can be formed to a thickness of,for example, from about 2 microns to about 4 microns. Openings 20 aextend through patterned insulative material 18 a to an upper surface ofconductive material 16 a. Three openings 20 a are formed in structure 10a of FIG. 13, in contrast to the two openings 20 formed in structure 10of FIG. 2.

[0077] Referring to FIG. 14, a conductive material 22 a is formed withinopenings 20 a to narrow the openings. Conductive material 22 a cancomprise the same material as conducive material 22 of FIGS. 2 and 3,and can be formed and patterned utilizing the methodology describedabove with reference to FIGS. 2 and 3.

[0078] A dielectric material 44 a is formed within openings 20 a.Dielectric material 44 a can comprise the same materials as describedabove for dielectric material 44 of FIG. 6.

[0079] The structure of FIG. 14 comprises three isolated conductivecontainer structures 200, 202, and 204. Structures 200 and 202 areanalogous to the structures 23 and 25 of FIG. 3, and structure 204 isultimately to comprise a conductive interconnect between conductivelayer 16 and other circuitry (not shown).

[0080] Referring to FIG. 15, dielectric material 44 a is patterned toremove the material from over conductive structure 204, while leavingthe material over conductive structures 200 and 202. Such patterning canbe accomplished by, for example, forming a patterned layer ofphotoresist over the dielectric material and subsequently transferring apattern from the patterned photoresist to the dielectric material byetching the dielectric material. The photoresist can then be removedfrom over the patterned dielectric material.

[0081] A conductive material 206 is formed within narrowed openings 20 aand over structures 200, 202 and 204. Conductive material 206 cancomprise, for example, conductively doped polysilicon.

[0082] Referring to FIG. 16, conductive material 206 is patterned toform storage node masses 46 a and 48 a, as well as to form a conductivemass 208 within and over conductive structure 204. The patterning ofconductive material 206 can be accomplished by, for example, forming apatterned layer of photoresist over material 206 and subsequentlytransferring a pattern from the photoresist to material 206 with an etchof material 206. The photoresist can then 11 be removed, to leave thestructures shown in FIG. 16. Storage node masses 46 a and 48 a, togetherwith dielectric material 44 a and conductive containers 200 and 202,define capacitor structures 50 a and 52 a.

[0083] Referring to FIG. 17, an insulative material 210 is formedbetween conductive structures 46 a, 48 a and 208; and over insulativematerial 18 a. Insulative material 210 can comprise, for example,silicon dioxide. Insulative material 210 can be formed betweenstructures 46 a, 48 a and 208 by forming the insulative material overand between structures 46 a, 48 a and 208, and subsequently planarizingthe insulative material to remove the insulative material from overstructures 46 a, 48 a and 208. A suitable planarization method ischemical-mechanical polishing. The planarization can also remove some ofconductive material 206 to form a planarized upper surface 212 whichextends across structures 46 a, 48 a and 208, as well as acrossinsulative regions 210.

[0084] Referring to FIG. 18, a dopant diffusion region 214 is formedbetween and within structures 46 a and 48 a. Diffusion region 214 can beformed by trenching into structures 46 a, 48 a and the intervening oxideregion, and subsequently filling the trench with a suitable material,such as, for example, silicon dioxide. The trench and refill can beanalogous to the trench and refill described with reference to FIGS.8-11, with the exception that the trenching of FIG. 18 has extended intothe insulative material 210, as well as into conductive structures 46 aand 48 a. The diffusion region 214, in contrast to the diffusion regions64 and 66, preferably comprises an insulative dopant barrier material toavoid shorting between nodes 46 a and 48 a.

[0085] After dopant isolation region 214 is formed, an upper surface offragment 10 a is planarized to form a planarized upper surface 62 aanalogous to the planarized upper surfaces 62 of FIG. 10.

[0086] Referring to FIG. 19, an amorphous silicon layer 70 a is formedover planarized upper surfaces 62 a, and a base 72 a is bonded overamorphous silicon layer 70 a. Subsequently, transistor gates 100 a and102 a (shown more schematically than transistor gates 100 and 102 ofFIG. 12, but which can comprise the same layers as transistors 100 and102 of FIG. 12) are formed over base 72 a. Source/drain regions 136 a,138 a and 140 a are formed within base 72 a, and lightly doped regions110 a, 112 a and 114 a are formed adjacent the transistor gates.Sidewall spacers are not shown adjacent transistor gates 100 a an 102 a,but it is to be understood that spacers similar to the spacers 116 ofFIG. 12 could be formed adjacent one or both of gates 100 a and 102 a.Isolation regions 271 and 273 are also formed within base 72 a, withisolation region 271 being adjacent source/drain region 136 a, andisolation region 273 being between source/drain region 140 a and aconductively doped region 250. Isolation regions 271 and 273 can beformed by, for example, forming trenches within base 72 a and fillingthe trenches with silicon dioxide.

[0087] An insulative material 230 is formed over gates 100 a and 102 a,and a conductive bitline interconnect 232 is formed to extend throughinsulative material 230 and to source/drain region 138. Conductiveinterconnect 232 is shown comprising a pair of conductive layers (231and 233), with an outer layer 233 being, for example, a metal nitride,such as, for example, titanium nitride; and an inner layer 231 being,for example, a metal, such as, for example, tungsten. A bitline 240 isshown formed and patterned over insulative material 230.

[0088] Conductively doped region 250 which forms a conductiveinterconnect through base 72 a and to conductive material 208. A contact252 is shown extending through insulative material 230 and to dopedregion 250. Contact 252 is shown comprising the conductive materials 231and 233 described previously with reference to bitline contact 232.Also, an electrical connection 260 is shown formed and patterned overcontact 252. Electrical connection 260 is utilized to provide voltage toconductive layer 16 a (through conductive materials 252, 250, 208 and204), and accordingly to power a capacitor plate associated withcapacitor structures 50 a and 52 a.

[0089] Another embodiment of the present invention is described withreference to FIGS. 20-24. In describing the embodiment of FIGS. 20-24,similar numbering will be utilized as was used above in describing theembodiment of FIGS. 1-12, with the suffix “b” utilized to indicatestructures in FIGS. 20-24.

[0090] Referring to FIG. 20, a fragment 10 b comprises a base 12 bhaving an insulative layer 14 b and a conductive layer 16 b formedthereover. Base 12 b, insulative layer 14 b and conductive layer 16 bcan comprise the same materials as described above for structures 12, 14and 16 of FIG. 1.

[0091] A second conductive material 300 is formed over and on firstconductive material 16 b. Second conductive material 300 can comprisethe same composition as first conductor material 16 b, and specificallycan comprise one or more of metal, metal silicide or conductively dopedsilicon (such as, for example, conductively-doped polysilicon).Conductive material 300 is patterned as pedestals, which formprojections 302, 304 and 306 extending from about 1 micron to about 4microns above an upper surface of conductive material 16 b. Material 300can be patterned into the pedestals 302, 304 and 306 by, for example,forming a layer of material 300 over layer 16 b, and subsequentlypatterning the layer of material 300 by providing a patterned layer ofphotoresist over the material 300 and transferring a pattern from thephotoresist to material 300 with a suitable etch. The photoresist canthen be removed to leave patterned structures 302, 304 and 306.Projections 302, 304 and 306 comprise sidewalls 303, 305 and 307,respectively. Further, projections 302, 304 and 306 comprise uppersurfaces 308, 310 and 312, respectively.

[0092] A dielectric material 44 b is formed over projections 302 and304, and specifically is formed along the sidewalls and over the topsurfaces of the projections. Dielectric material 44 b can comprise thesame compositions as described above for dielectric material 44 of FIG.6. Dielectric material 44 b is patterned such that it extends alongsidewalls of projection 306, but does not extend over a top surface ofprojection 306.

[0093] A conductive material 320 is formed over dielectric material 44b.

[0094] Referring to FIG. 21, masking structures 330 are formed overconductive pedestals 302, 304 and 306. Masking structures 330 compriseinner blocks 320 and sidewall spacers 322 formed along sidewalls of theblocks 320. Blocks 320 and sidewalls spacers 322 preferably bothcomprise the same material. A suitable material is silicon dioxide.Blocks 320 are preferably formed utilizing a same pattern as wasutilized for patterning projections 302, 310 and 312. Accordingly,blocks 320 will have an identical width as projections 302, 304, and306. Subsequently, spacers 322 are formed alongside the blocks bydepositing and anisotropically etching a material. Accordingly, thecombination of blocks 320 and spacers 322 forms patterning structures330 having a width greater than the width of projections 302, 304 and306.

[0095] Referring to FIG. 22, patterning structures 330 (FIG. 21) areutilized to pattern conductive material 320 into storage node masses 46b and 48 b, as well as into a conductive interconnect 350.

[0096] Subsequently, an insulative material 352 is formed betweenstructures 46 b, 48 b and 350. Insulative material 352 can be formed by,for example, depositing an insulative material over and betweenstructures 46 b, 48 b and 350, and subsequently planarizing theinsulative material 352 to remove the insulative material from overstructures 46 b, 48 b and 350. The planarization can comprise, forexample, chemical-mechanical polishing, and forms a planarized uppersurface 353. It is noted that the planarization can also remove some ofconductive material 320 during the formation of planarized upper surface353.

[0097] Structure 46 b defines a storage node mass, and together withprojection 302 and dielectric material 44 b defines a first capacitorstructure 50 b. Likewise, structure 48 b defines a second storage nodemass, and together with projection 304 and dielectric material 44 bdefines a second capacitor structure 52 b. Note that conductive material16 b forms a cell plate conductively connected with projections 302 band 304 b. Conductive structure 350 forms a conductive interconnect fortransferring voltage to the cell plate.

[0098] Referring to FIG. 23, a dopant barrier layer 354 is formed withinand between storage node masses 46 b and 48 b. Dopant barrier layer 354can be formed utilizing procedures described above with reference toformation of dopant barrier layer 214 in FIG. 18.

[0099] After dopant barrier layer 354 is formed, an upper surface ofbarrier layer 354 is planarized together with upper surfaces ofconductive masses 46 b, 48 b and 350, as well as an upper surface ofinsulative material 352, to form a planarized upper surface 62 b.

[0100] Referring to FIG. 24, an amorphous silicon layer 70 b is formedover planarized upper surface 62 b and subsequently structures analogousto those described with reference to FIG. 19 are formed over amorphoussilicon layer 70 b. The structures shown in FIG. 24 are labeledanalogously to those of FIG. 19, with the suffix “b” utilized toindicate structures shown in FIG. 24.

[0101] It is noted that among the advantages of the structures of thepresent invention relative to prior art devices is that the capacitorsof the devices of the present invention (for instance, capacitors 56 and58 of FIG. 12) can be electrically isolated from a bottommonocrystalline substrate (for instance, 12 of FIG. 12). Thus, there isincreased tolerance for defects in the bottom monocrystalline substrate.Additionally, static refresh can remain non-degraded by the storage nodejunction, and accordingly devices of the present invention can haveadvantages of SOI, without being conventional SOI structures.

[0102] A fourth embodiment method of the present invention is describedwith reference to FIGS. 25-33. Referring initially to FIG. 25, asemiconductor wafer fragment 500 is shown at an initial processing step.Wafer fragment 500 comprises a substrate 502. Substrate 502 cancomprise, for example, a monocrystalline silicon wafer lightly dopedwith a background p-type dopant. Substrate 502 further comprises adamage region 504 formed therein, and represented by a dashed line.Damage region 504 can be formed by implanting one or more isotopes ofhydrogen into substrate 502. Damage region 504 will ultimately beutilized for making a so-called “smart cut” within wafer 502. Damageregion 504 can be formed within substrate 502 by, for example, a onetime dose with deuterium to form the deuterium to an implant depth offrom about 3000 Angstroms to about 10000 Angstroms beneath an uppersurface 506 of substrate 502. The deuterium dose can be to from about3×10¹⁶ atoms/cm³ to about 7×10¹⁶ atoms/cm³.

[0103] One aspect of the processing described with reference to thisfourth embodiment is that such processing should preferably comprisethermal energies which are sufficiently low that the hydrogen isotopeswithin damage region 504 are not excessively diffused within substrate502. Specifically, a total sequence thermal budget preferably remainsless or equal to 750° C. for three hours to prevent dispersion of thehydrogen isotopes from the defect layer.

[0104] Substrate 502 preferably comprises a low oxygen content, to avoidoxygen precipitation, with a preferable oxygen content being less than24 ppm.

[0105] A nitride layer 510 is formed over substrate 502, and separatedfrom the substrate by an oxide layer 508. Oxide layer 508 is a pad layerthat alleviates stress that could otherwise be created by having nitridelayer 510 directly on substrate 502. Nitride layer 510 can comprise, forexample, Si₃N₄, and oxide layer 508 can comprise, for example, SiO₂.Nitride layer 510 can function as an etch stop layer in particularprocessing of the present invention, and accordingly can be referred toas etch stop layer 510.

[0106] A photoresist layer 512 is formed over nitride layer 510 andpatterned to have openings 514 extending therethrough. Photoresist layer512 can be patterned by photolithographic patterning. A dopant isimplanted through openings 514 and into substrate 502 to formconductively doped diffusion regions 516. The dopant can comprise eithern-type dopant or p-type dopant.

[0107] Referring to FIG. 26, oxide layer 508 and nitride layer 510 areetched to extend openings 514 to upper surface 506 of substrate 502.

[0108] Referring to FIG. 27, photoresist 512 (FIG. 26) is removed.Subsequently, an insulative material layer 518 is formed over substrate502, and a sacrificial layer 520 is formed over layer 518. Layer 518 cancomprise, for example, silicon dioxide, and can be formed by, forexample, chemical vapor deposition using tetraorthosilicate (TeOS).Sacrificial layer 520 can comprise, for example, borophosphosilicateglass (BPSG).

[0109] Referring to FIG. 28, openings 522, 524, 526 and 528 are etchedthrough layers 518 and 520. Openings 522, 524, 526 and 528 can be formedby, for example, photolithographic processing utilizing photoresist (notshown), and an oxide etch. Openings 522, 524, 526 and 528 extend toupper surface 506 of substrate 502 to contact diffusion regions 516.Openings 522, 524, 526 and 528 also stop on etch stop layer 510.Accordingly, openings 524 and 526 comprise lowermost portions which arenarrower than upper portions above the lowermost portions (with thelowermost portions being between layer 510 and 518, as well as betweenlayer 508 and 518; and with the upper portions being between thematerial 520 one side of an opening and the material 520 on an otherside of the opening).

[0110] Referring to FIG. 29, openings 522, 524, 526 and 528 (FIG. 28)are filled with a first conductive material 530. Material 530 cancomprise, for example, conductively doped polysilicon. Material 530 isshown having a planarized upper surface 532. Such planarized uppersurface can be formed by, for example, chemical-mechanical polishing.

[0111] Referring to FIG. 30, sacrificial material 520 (FIG. 29) isremoved from between stacks of conductive material 530 to defineopenings 534, 536 and 538, and also to define isolated conductivestructures 540, 542, 544 and 546. The removal of sacrificial material520 is shown to leave insulative material 518. Such can be accomplishedutilizing, for example, a timed etch which is stopped after material 520is removed.

[0112] Conductive structures 540, 542, 544 and 546 have uppermostsurfaces defined by planarized upper surface 532 and have sidewallsexposed within openings 534, 536 and 538.

[0113] Referring to FIG. 31, a dielectric material 550 is formed overupper surfaces 532 of conductive structures 540, 542, 544 and 546, aswell as along the sidewalls of the conductive structures. Dielectricmaterial 550 an comprise, for example, one or both of silicon dioxideand silicon nitride, and in particular examples can comprise a layer ofsilicon nitride sandwiched between a pair of silicon dioxide layers (aso-called ONO structure).

[0114] A second conductive material 552 is formed over dielectricmaterial 550 and spaced from first conductive material 530 by dielectricmaterial 550. Second conductive material 552 can comprise, for example,conductively doped polysilicon. Material 552 comprises a planarizedupper surface 554 which can be formed by, for example,chemical-mechanical polishing.

[0115] In the shown embodiment, a conductive interconnect 555 is shownformed to extend through dielectric layer 550, and to connect secondconductive material 552 with conductive structure 546. Conductiveinterconnect 555 can be formed by initially forming an opening 553extending through layer 550, and subsequently filling opening 553 withconductive material (such as, for example, conductively dopedpolysilicon).

[0116] A silicide layer 556 is shown formed over layer 554, and canenhance electrical conduction across conductive material 552. Silicide556 can comprise, for example, titanium silicide or tungsten silicide.

[0117] An oxide bonding region 558 is shown formed over silicide 556.Oxide bonding region 558 can comprise, for example, silicon dioxide; andspecifically can be formed from two combined regions (shown as 560 and562) that each comprise silicon dioxide.

[0118] A second silicon wafer 564 is shown bonded through oxide bondingregion 558, and provides a “handle” for manipulating wafer 500 duringsubsequent processing. The bonding of wafer 564 can be accomplished asfollows. Wafer 564 and oxide region 562 can be initially provided as adiscrete structure; and oxide region 560 can initially be provided to beassociated only with the structures over substrate 502. Subsequently,oxide region 562 can be bonded to oxide region 560 by a process whichincludes, for example, contacting oxide layers 560 and 562 with oneanother, and heating the oxide layers to a temperature of about 550° C.for a time of about 30 minutes.

[0119] Referring to FIG. 32, wafer 500 is shown in an invertedorientation relative to FIG. 31. The orientation of wafer fragment 500is inverted so that subsequent devices can be formed on substrate 502.Substrate 502 has been cleaved along defect region 504 (FIG. 31). 8 Suchcleavage can occur utilizing, for example, thermal processing. After thecleavage, substrate 502 is planarized to bring an upper surface 570 ofthe shown fragment 500 down to a level of diffusion regions 516 (thepolishing can remove, for example, from 0.3 microns to 0.8 microns ofmaterial). Subsequently, trenches are formed within substrate 502 andfilled insulative material 572 to define isolation regions extendingwithin diffusion regions 516. The isolation regions defined byinsulative material 572 effectively split each of the diffusion regions516 into two isolated regions. The trenches in diffusion regions 516 canbe formed by, for example, masking with pattern photoresist (not shown),and a subsequent etch into substrate 502 to a depth of, for example,about 3000 Å. The trenches can then be filled with insulative materialby, for example, chemical vapor depositing silicon dioxide within thetrenches. Subsequently, the wafer 500 can be subjected tochemical-mechanical polishing to clear the insulative material from overupper surface 570, as well as to planarize an upper surface of theremaining insulative material 572.

[0120] Referring to FIG. 33, a thin oxide layer 580 is formed oversurface 570. Oxide layer 580 can comprise, for example, silicon dioxide,and can be formed by chemical vapor deposition.

[0121] Wordline structures 582, 584, 586, 588, 590 and 592 are formedover thin oxide layer 580. The wordline structures can comprise, forexample, one or more conductive materials such as, for example,polysilicon, metal silicide and metal. An exemplary wordline structurecomprises a stack of polysilicon, tungsten silicide and tungsten metal.Also, insulative material caps can be formed on top of the stacks, andsidewall spacers can be formed adjacent the stacks. The wordlinestructures are shown schematically to simplify the drawing of FIG. 33.The wordline structures can be formed utilizing conventional depositionand patterning methods.

[0122] After formation of the wordline structures, a mask (not shown)can be formed over wordline structures 582, 584, 590 and 592, whileimplanting a dopant adjacent structures 586 and 588 to form lightlydoped diffusion regions 600, 602 and 604. Diffusion regions 600, 602 and604 can also be heavily doped. The dopant utilized for regions 600, 602and 604 can be n-type or p-type. Lines 586 and 588, together withdiffusion regions 600, 602 and 604, define a pair of transistorstructures for which the lines comprise transistor gates. Specifically,line 586 gatedly connects regions 600 and 602 to define a transistorstructure, and line 588 gatedly connects regions 602 and 604 to define atransistor structure.

[0123] An insulative material 606 is formed over oxide layer 580, aswell as over the wordlines. Insulative material 606 can comprise, forexample, BPSG.

[0124] A conductive structure 608 is formed through insulative layer 606to diffusion region 602. Conductive structure 608 can comprise one ormore conductive materials, and in the shown embodiment comprises a firstconductive material 610 and a second conductive material 612. Firstconductive material 610 can comprise, for example, titanium nitride, andsecond conductive material 612 can comprise, for example, titanium.Conductive structure 608 can be formed within insulative material 606by, for example, patterning an opening into material 606 andsubsequently filling the opening with conductive material. Theconductive material can subsequently be subjected to chemical-mechanicalpolishing to remove the material from over insulative layer 606, as wellas to planarize a upper surface of insulative material 606.

[0125] After planarization of an upper layer of insulative material 606,a conductive material such as, for example, aluminum metal can be formedacross an upper surface of layer 606 to form conductive line 614. Thestructure shown in FIG. 33 comprises a pair of DRAM structures.Specifically, a transistor gate comprised by line 586 is electricallyconnected through diffusion region 600 with a capacitor structure 616defined by conductive structure 544 in combination with dielectricmaterial 550 and second conductive material 552. Also, a transistor gatedefined by line 588 is connected through diffusion regions 604 and 516with a capacitor structure 618 defined by conductive structure 542 incombination with dielectric material 550 and second conductive material552.

[0126] A conductive interconnect 618 is shown in electrical connectionwith second conductive material 552 through interconnect 555. Conductiveinterconnect 618 can be formed by, for example, forming an openingthrough oxide layer 580, and subsequently filling the opening withconductive material. Interconnect 618 can be connected to an electricalsource 620 and utilized to provide power to second conductive material552, and accordingly, to power a capacitor plate defined by material552.

[0127] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a DRAM cell, comprising: forming a firstsubstrate comprising first DRAM sub-structures separated from oneanother by an insulative material; providing a second semiconductorsubstrate comprising a monocrystalline material; after forming the firstDRAM substructures, bonding the second semiconductor substrate to thefirst substrate; and forming second DRAM sub-structures supported by oneor both of the first and second substrates and in electrical connectionwith the first DRAM sub-structures, one of the first and second DRAMsubstructures being transistor gate structures and the other of thefirst and second DRAM sub-structures being capacitor structures.
 2. Themethod of claim 1 wherein the first DRAM substructures are capacitorstructures and the second DRAM sub-structures are transistor gatestructures.
 3. The method of claim 1 wherein the first DRAMsubstructures are capacitor structures and the second DRAMsub-structures are transistor gate structures; and wherein the secondsubstrate is bonded beneath the capacitor structures and the transistorgate structures are bonded above the capacitor structures.
 4. The methodof claim 1 wherein the first DRAM substructures are capacitor structuresand the second DRAM sub-structures are transistor gate structures; andwherein the second substrate is bonded over the capacitor structures andthe transistor gate structures are bonded over the second substrate. 5.A method of forming a DRAM cell, comprising: forming a first substratecomprising first DRAM sub-structures separated from one another by aninsulative material; the first DRAM sub-structures defining an uppersurface; forming a second semiconductor substrate comprising amonocrystalline material; bonding the second semiconductor substrate tothe first substrate above the first DRAM sub-structures; and formingsecond DRAM sub-structures on the second substrate and in electricalconnection with the first DRAM sub-structures, one of the first andsecond DRAM sub-structures being transistor gate structures and theother of the first and second DRAM sub-structures being capacitorstructures.
 6. The method of claim 5 wherein the first DRAMsubstructures are capacitor structures and the second DRAMsub-structures are transistor gate structures.
 7. The method of claim 6wherein the transistor gate structures are electrically connected to thecapacitor structures through source/drain regions which extend throughthe second semiconductor substrate.
 8. The method of claim 5 furthercomprising forming a silicon-containing layer over the first DRAMsub-structures, and wherein the bonding the second semiconductorsubstrate comprises bonding the second semiconductor substrate to thesilicon-containing layer.
 9. The method of claim 8 wherein thesilicon-containing layer comprises amorphous silicon.
 10. The method ofclaim 8 wherein the silicon-containing layer consists essentially ofamorphous silicon.
 11. The method of claim 8 wherein thesilicon-containing is formed to consist essentially of undoped amorphoussilicon.
 12. The method of claim 8 further comprising planarizing anupper surface of the silicon-containing layer before bonding the secondsemiconductor substrate to the silicon-containing layer.
 13. The methodof claim 8 further comprising planarizing an upper surface of the firstsubstrate before forming the silicon-containing layer.
 14. The method ofclaim 8 wherein the first DRAM substructures comprise conductively dopedsilicon, and further comprising: forming a dopant barrier material overat least a portion of the first DRAM sub-structures; and forming thesilicon-containing layer over the dopant barrier material.
 15. Themethod of claim 8 wherein the first DRAM substructures compriseconductively doped silicon, and further comprising: forming at least onetrench within the first DRAM substructures; filling the at least onetrench with a dopant barrier material; planarizing an upper surface ofthe first DRAM subs-structures and dopant barrier material; and formingthe silicon-containing layer over the planarized upper surface.
 16. Amethod of forming a DRAM cell, comprising: forming a cell plate layer;forming a dielectric material over the cell plate layer; forming aconductive storage node mass over the dielectric material; theconductive storage node mass, dielectric material and cell plate layertogether defining a capacitor structure, a first substrate being definedto encompass the capacitor structure; bonding a monocrystalline siliconsubstrate to the first substrate and over the storage node mass; andforming a transistor gate on the monocrystalline silicon substrate andoperatively connected with the capacitor structure to define a DRAMcell.
 17. The method of claim 16 further comprising forming asilicon-containing layer over the first capacitor structure, and whereinthe bonding the monocrystalline silicon substrate comprises bonding themonocrystalline silicon substrate to the silicon-containing layer. 18.The method of claim 16 wherein the forming the cell plate layercomprises: forming a conductive material layer over an insulativematerial base; and forming at least one conductive projection extendingupwardly from the conductive material layer.
 19. The method of claim 18wherein the at least one conductive projection comprises a differentconductive material than the conductive material layer.
 20. The methodof claim 16 wherein the forming the cell plate layer comprises: forminga first conductive material layer over an insulative material base;forming a second conductive material over the first conductive material;and patterning the second conductive material layer into a conductiveprojection extending upwardly from the first conductive material layer.21. The method of claim 16 wherein the forming the cell plate layercomprises: forming a first conductive material layer over an insulativematerial base; forming a second conductive material over the firstconductive material; and patterning the second conductive material layerinto a conductive projection extending upwardly from the firstconductive material layer, the conductive projection comprising a topsurface and sidewall surfaces extending from the first conductivematerial layer to the top surface; the method further comprising:forming the dielectric material over the top surface and along thesidewall surfaces; and forming the storage node mass over the topsurface and along the sidewall surfaces.
 22. The method of claim 21further comprising: after forming the dielectric material layer, forminga second conductive material layer over the dielectric material layer;forming a patterned mask over the second conductive material layerutilizing a same pattern as that utilized to form the conductiveprojection; forming sidewall spacers along sidewall edges of thepatterned mask by: depositing a sidewall spacer material over thepatterned mask and second conductive material, and anisotropicallyetching the sidewall spacer material; and patterning the secondconductive material with the mask and sidewall spacers to form thestorage node mass.
 23. The method of claim 16 wherein the forming thecell plate layer comprises: forming a first conductive material layerover an insulative material base; forming a first insulative layer overthe first conductive material layer, the first insulative layer havingan opening extending therethrough to the first conductive materiallayer; and forming a second conductive material within the opening todefine at least one conductive projection extending upwardly from thefirst conductive material layer.
 24. The method of claim 23 wherein thesecond conductive material only partially fills the opening and definestwo conductive projections extending upwardly from the first conductivematerial layer.
 25. The method of claim 23 wherein the second conductivematerial is formed within the opening and over the first insulativelayer, and further comprising removing the second conductive materialfrom over the first insulative layer.
 26. The method of claim 23wherein: the second conductive material only partially fills the openingand defines two conductive projections extending upwardly from the firstconductive material layer, the second conductive material narrowing theopening; a protective material is formed over the second conductivematerial within the narrowed opening; after forming the protectivematerial, the second conductive material is removed from over the firstinsulative layer; and after removing the second material from over thefirst insulative layer, the protective material is removed from withinthe narrowed opening.
 27. The method of claim 26 wherein the protectivematerial comprises photoresist.
 28. The method of claim 26 furthercomprising: after removing the protective material from within thenarrowed opening, forming a second insulative layer over the firstinsulative layer and within the narrowed opening: patterning the firstand second insulative layers to remove the second insulative layer fromwithin the narrowed opening and to remove at least some of the firstinsulative layer from along sidewalls of the conductive projections, theremoving of the first insulative layer from along the sidewalls definingexposed sidewall portions of the conductive projections; forming thedielectric material along the exposed sidewall portions and within thenarrowed opening; and forming the conductive storage node mass along theexposed sidewall portions and within the narrowed opening.
 29. A methodof forming at least two DRAM cells, comprising: forming a firstsubstrate comprising a first conductive material layer; forming at leasttwo separate conductive projections on and electrically connected withthe first conductive material layer, the conductive projections andfirst conductive material layer together defining a cell plate for atleast two separate capacitor structures; forming a dielectric materialover the conductive projections; forming at least two separateconductive capacitor storage node masses over the conductive projectionsand spaced from the conductive projections by the dielectric material;the conductive storage node masses, dielectric material and conductiveprojections together defining at least two separate capacitorstructures; forming a silicon-containing layer over the conductivestorage node masses and electrically connected with the storage nodemasses; bonding a monocrystalline silicon substrate to thesilicon-containing layer; and forming transistor gates on themonocrystalline silicon substrate and operatively connected with the atleast two capacitor structures through the silicon-containing layer todefine at least two DRAM cells.
 30. The method of claim 29 wherein atleast one of the transistor gates has a channel region within themonocrystalline silicon directly above at least one of the storagemasses, and further comprising, before forming the silicon layer,forming a dopant barrier material over at least a portion of the atleast one of the storage masses to inhibit dopant migration from the atleast one of the storage masses into the channel region.
 31. The methodof claim 30 wherein the dopant barrier material comprises silicondioxide.
 32. The method of claim 29 wherein at least one of thetransistor gates has a channel region within the monocrystalline silicondirectly above at least one of the storage masses, and furthercomprising, before forming the silicon layer: etching into the at leastone of the storage masses to form a trench; and forming a dopant barriermaterial within the trench to inhibit dopant migration from the at leastone of the storage masses into the channel region.
 33. The method ofclaim 32 wherein the dopant barrier material consists essentially ofsilicon dioxide.
 34. The method of claim 29 wherein at least one of thetransistor gates has a channel region within the monocrystalline silicondirectly above a first portion of one of the storage masses, and has asource/drain region within the monocrystalline silicon directly above asecond portion of said one of the storage masses, the method furthercomprising: forming a dopant barrier material over the first portion ofthe storage mass to inhibit dopant migration from the first portion ofthe one of the storage masses into the channel region, themonocrystalline silicon substrate being formed over the dopant barriermaterial; and forming a conductive interconnect between the source/drainregion and the second portion of the at least one of the storage masses.35. The method of claim 34 wherein the conductive interconnect comprisesa conductively doped region extending vertically through thesilicon-containing layer from the source/drain region to the secondportion of the at least one of the storage masses.
 36. The method ofclaim 29 wherein at least one of the transistor gates has a channelregion within the monocrystalline silicon directly above a first portionof one of the storage masses, and has a source/drain region within themonocrystalline silicon directly above a second portion of said one ofthe storage masses, the method further comprising: etching into thefirst portion of the one of the storage masses to form a trench; forminga dopant barrier material within the trench to inhibit dopant migrationfrom the first portion of the one of the storage masses into the channelregion, the silicon-containing layer being formed over the dopantbarrier and the second portion of the one of the storage masses; andforming a conductive interconnect between the source/drain region andthe second portion of the at least one of the storage masses.
 37. Themethod of claim 36 wherein the conductive interconnect comprises aconductively doped region extending vertically through thesilicon-containing layer from the source/drain region to the secondportion of the at least one of the storage masses.
 38. A method offorming a DRAM cell, comprising: forming a first substrate having adamage region therein; forming at least one capacitor structuresupported by the first substrate; after forming the capacitor structure,breaking the first substrate along the damage region; after breaking thefirst substrate; bonding a monocrystalline silicon substrate to thefirst substrate; and after bonding the monocrystalline substrate to thefirst substrate, forming a transistor gate over the capacitor structureand electrically connected with the capacitor structure to define a DRAMcell.
 39. The method of claim 38 wherein the forming the capacitorstructure comprises: forming a diffusion region within the firstsubstrate; forming a conductive storage node over the first substrateand electrically connected with the diffusion region; forming adielectric layer over the conductive storage node; and forming aconductive cell plate over the dielectric layer.
 40. The method of claim38 wherein the forming the capacitor structure comprises: forming adiffusion region within the first substrate; forming an etch stop layerover at least a portion of the first substrate; patterning the etch stoplayer to form an opening extending through the etch stop layer and toexpose a portion -of the first substrate within the opening, thediffusion region being within the exposed portion of the firstsubstrate; forming an insulative material layer over the etch stop layerand within the opening; forming a sacrificial material layer over theinsulative material layer; forming an opening extending through thesacrificial material layer and the insulative material layer to expose aportion of the diffusion region; forming a first conductive materialwithin the opening; removing the sacrificial material from over theinsulative material to expose a sidewall of the first conductivematerial; forming a dielectric material on an upper surface of theconductive material and along the exposed sidewall; and forming a secondconductive material over the dielectric material and spaced from thefirst conductive material by the dielectric material.
 41. The method ofclaim 40 wherein the etch stop layer comprises silicon nitride.
 42. Themethod of claim 40 wherein the forming the insulative material layercomprises chemical vapor deposition of silicon dioxide from TeOS. 43.The method of claim 40 wherein the sacrificial material comprises BPSG.44. A method of forming at least two DRAM cells, comprising: forming afirst substrate having a damage region therein; forming at least twoseparated capacitor structures supported by the first substrate; afterforming the capacitor structures, breaking the first substrate along thedamage region; after breaking the first substrate; bonding amonocrystalline silicon substrate to the first substrate; and afterbonding the monocrystalline silicon substrate to the first substrate,forming two or more transistor gates operatively connected with thecapacitor structures to define at least two DRAM cells.
 45. The methodof claim 44 wherein the monocrystalline silicon substrate is bondedbeneath the capacitor structures and the transistor gates are formedover the capacitor structures.
 46. The method of claim 44 wherein theforming the capacitor structures comprises: forming diffusion regionswithin the first substrate; forming an etch stop layer over at least aportion of the first substrate; patterning the etch stop layer to form apair of openings extending through the etch stop layer and to exposeportions of the first substrate within the openings, the diffusionregions being within the exposed portions of the first substrate;forming an insulative material layer over the etch stop layer and withinthe openings; forming a sacrificial material layer over the insulativematerial layer; forming a pair of openings extending through thesacrificial material layer and the insulative material layer to exposeportions of the diffusion regions; forming a first conductive materialwithin the openings; removing the sacrificial material from over theinsulative material to expose sidewalls of the first conductivematerial; forming a dielectric material on an upper surface of theconductive material and along the exposed sidewalls; and forming asecond conductive material over the dielectric material and spaced fromthe first conductive material by the dielectric material.
 47. A DRAMcell, comprising: a first monocrystalline silicon substrate comprising aDRAM capacitor formed thereover; a second monocrystalline substratejoined to the first substrate beneath the capacitor structures andseparated from the first substrate by an oxide bonding region; and aDRAM transistor gate over the DRAM capacitor and electrically connectedwith the DRAM capacitor.
 48. A DRAM cell, comprising: a capacitor; aninsulative material over a portion of the capacitor; an amorphoussilicon layer over the insulative material; and a transistor structureover the capacitor, the transistor structure comprising a gate over theinsulative material and a source/drain region proximate the gate, thesource/drain region being electrically connected with the DRAM capacitorthrough the amorphous silicon layer.
 49. A DRAM cell, comprising: acapacitor comprising a storage node, a cell plate, and a dielectricmaterial between the storage node and cell plate;; a transistorstructure over the capacitor and in electrical connection with thecapacitor; and an electrically conductive path beside the storage nodeand extending through the dielectric material to the cell plate, theelectrically conductive path providing power to the cell plate.
 50. ADRAM assembly, comprising: a first substrate comprising first DRAMsub-structures separated from one another by an insulative material; thefirst DRAM substructures defining an upper surface; a secondsemiconductor substrate comprising a monocrystalline material and bondedto the first substrate above the first DRAM substructures; and secondDRAM sub-structures on the second substrate and in electrical connectionwith the first DRAM sub-structures, one of the first and second DRAMsub-structures being transistor gate structures and the other of thefirst and second DRAM sub-structures being capacitor structures.
 51. Theassembly of claim 50 wherein the first DRAM substructures are capacitorstructures and the second DRAM sub-structures are transistor gatestructures.
 52. The assembly of claim 51 wherein the transistor gatestructures are electrically connected to the capacitor structuresthrough source/drain regions which extend through the secondsemiconductor substrate.
 53. The assembly of claim 50 further comprisinga silicon-containing layer over the first DRAM sub-structures, andwherein the second semiconductor substrate. is bonded on thesilicon-containing layer.
 54. The assembly of claim 53 wherein thesilicon-containing layer comprises amorphous silicon.
 55. The assemblyof claim 53 wherein the silicon-containing layer consists essentially ofamorphous silicon having conductively doped regions extendingtherethrough.
 56. The assembly of claim 53 wherein the first DRAMsubstructures comprise conductively doped silicon, and furthercomprising: a dopant barrier material over at least a portion of atleast one of the first DRAM sub-structures; and the silicon-containinglayer being over the dopant barrier material.
 57. A semiconductorstructure, comprising: a cell plate layer; a dielectric material overthe cell plate layer; a conductive storage node mass over the dielectricmaterial; the conductive storage node mass, dielectric material and cellplate layer together defining a capacitor structure, a first substratebeing defined to encompass the capacitor structure; a monocrystallinesilicon substrate bonded to the first substrate and over the storagenode mass; and a transistor gate on the monocrystalline siliconsubstrate and operatively connected with the capacitor structure todefine a DRAM cell.
 58. The structure of claim 57 further comprising asilicon-containing layer over the first capacitor structure, and whereinthe monocrystalline silicon substrate is bonded on thesilicon-containing layer.
 59. The structure of claim 58 wherein thesilicon-containing layer comprises amorphous silicon.
 60. The structureof claim 58 wherein the silicon-containing layer consists essentially ofamorphous silicon having conductively doped regions extendingtherethrough.
 61. The structure of claim 57 wherein the cell plate layercomprises: a conductive material layer over an insulative material base;and at least one conductive projection extending upwardly from theconductive material layer.
 62. The structure of claim 61 wherein the atleast one conductive projection comprises a different conductivematerial than the conductive material layer.
 63. The structure of claim57 wherein the cell plate layer comprises: a first conductive materiallayer over an insulative material base; a second conductive materialover the first conductive material and defining a conductive projectionextending upwardly from the first conductive material layer, theconductive projection comprising a top surface and sidewall surfacesextending from the first conductive material layer to the top surface;the structure further comprising: the dielectric material extending overthe top surface and along the sidewall surfaces; and the storage nodemass extending over the top surface and along the sidewall surfaces. 64.A semiconductor structure, comprising: a first substrate comprising afirst conductive material layer; at least two separate conductiveprojections on and electrically connected with the first material layer,the conductive projections and first conductive material layer togetherdefining a cell plate for at least two separate capacitor structures; adielectric material over the conductive projections; at least twoseparate conductive capacitor storage node masses over the conductiveprojections and spaced from the conductive projections by the dielectricmaterial; the conductive storage node masses, dielectric material andconductive projections together defining at least two separate capacitorstructures; a silicon-containing layer over the conductive storage nodemasses and electrically connected with the storage node masses; amonocrystalline silicon substrate bonded onto the silicon-containinglayer; and transistor gates on the monocrystalline silicon substrate andoperatively connected with the at least two capacitor structures todefine at least two DRAM cells.
 65. The structure of claim 64 whereinthe silicon-containing layer comprises amorphous silicon.
 66. Thestructure of claim 64 comprising source/drain regions within themonocrystalline silicon substrate proximate the transistor gates, thesource/drain regions being directly above at least at least part of theconductive masses and being electrically connected to the conductivemasses through vertically extending conductive interconnects.
 67. Thestructure of claim 66 wherein the silicon-containing layer consistsessentially of amorphous silicon having conductively doped regionsextending therethrough, the conductively doped regions being theconductive interconnects.
 68. The structure of claim 64 wherein at leastone of the transistor gates has a channel region within themonocrystalline silicon directly above at least one of the storagemasses, and further comprising a dopant barrier material over at least aportion of the at least one of the storage masses to inhibit dopantmigration from the at least one of the storage masses into the channelregion.
 69. The structure of claim 68 wherein the dopant barriermaterial consists essentially of silicon dioxide.